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| [JETCAS'24] | OpenPiton4HPC: Optimizing OpenPiton Towards High Performance Manycores. N. Leyva, A. Monemi, N. Oliete-Escuín, G. López-Paradís, X. Abancens, J. Balkind, E. Vallejo, M. Moretó and L. Alvarez. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. (IF: 3.7 in 2023, Q2, h5=41). [PDF] [DOI] | ||||
| [DT'22] | SynFull-RTL: Evaluation Methodology for RTL NoC Designs. N. Leyva, A. Monemi, and E. Vallejo. IEEE Design & Test. (IF: 2.0, Q3, h5=28). [PDF] [DOI] | ||||
| [TC'21] | S-SMART++: a low-latency NoC leveraging speculative bypass requests. I. Pérez, E. Vallejo, and R. Beivide. Transactions on Computers. (IF: 3.183, Tier A*, h5=56). [PDF] [DOI] | ||||
| [JSA'20] | Efficient Bypass in Mesh and Torus NoCs. I. Pérez, E. Vallejo, and R. Beivide. Journal of Systems Architecture. (IF: 3.777, Q1, Tier B, h5=22). [PDF] [DOI] | ||||
| [JPDC'19] | ACOR: Adaptive Congestion-Oblivious Routing in Dragonfly networks. M. Benito, P. Fuentes, E. Vallejo and R. Beivide. Journal of Parallel and Distributed Computing, September 2019. (IF: 2.296, Q2, Tier A*, h5=39). [PDF] [DOI] | ||||
| [CCPE'19] | Non-minimal Adaptive Routing Based on Explicit Congestion Notifications. M. Benito, E. Vallejo, C. Izu and R. Beivide. Concurrency and Computation: Practice and Experience, January 2019. (IF: 1.447, Q3, Tier A, h5=35). [Preprint] [DOI] [BIB] | ||||
| [CCPE'17] | A scalable synthetic traffic model of Graph500 for computer networks analysis. P. Fuentes, M. Benito, E. Vallejo, J. L. Bosque, R. Beivide, A. Anghel, G. Rodríguez, M. Gusat, C. Minkenberg, and M. Valero. Concurrency and Computation: Practice and Experience, December 2017. (IF: 1.114, Q3, Tier A, h5=35). [DOI] [BIB] | ||||
| [TPDS'17] | Projective Networks: Topologies for Large Parallel Computer Systems. C. Camarero, C. Martínez, E. Vallejo, and R. Beivide. IEEE Transactions on Parallel and Distributed Systems, July 2017. (IF: 3.971, Q1, Tier A*, h5=79). [PDF] [DOI] [REPOSITORY] [BIB] | ||||
| [SUPE'16] | Network Unfairness in Dragonfly Topologies. P. Fuentes, E. Vallejo, C. Camarero, R. Beivide, and M. Valero. The Journal of Supercomputing, December 2016. (IF: 1.326, Q2, Tier B, h5=32). [PDF] [DOI] [Document] [BIB] | ||||
| [SUPE'15] | On-the-Fly Adaptive Routing for dragonfly interconnection networks. M. García, E. Vallejo, R. Beivide, C. Camarero, M. Valero, G. Rodríguez, and C. Minkenberg. The Journal of Supercomputing, March 2015. (IF: 1.088, Q2, Tier B, h5=32). [Preprint] [DOI] [Repo] [BIB] | ||||
| [TACO'14] | Topological Characterization of Hamming and Dragonfly Networks and its Implications on Routing. C. Camarero, E. Vallejo and R. Beivide. ACM Transactions on Architecture and Code Optimization, December 2015. (IF: 0.503, Q4, Tier A, h5=23). [Preprint] [DOI] [BIB] | ||||
| [IJPP'11] | Hybrid Transactional Memory with Pessimistic Concurrency Control. E. Vallejo S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal and M. Valero. International Journal of Parallel Programming, June 2011. (IF: 0.569, Q3 , Tier A, h5=16). [Preprint] [DOI] [BIB] | ||||
| [TPDS'10] | Twisted Torus Topologies for Enhanced Interconnection Networks. J. M. Camara, M. Moretó, E. Vallejo, R. Beivide, J. Miguel, C. Martínez, and J. Navaridas. IEEE Transactions on Parallel and Distributed Systems, December, 2010 (IF: 1.575, Q2 , Tier A*, h5=76). [Preprint] [DOI] [BIB] | ||||
| [IJPP'06] | Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors. C. Martínez, E. Vallejo, R. Beivide, C. Izu and M. Moretó. International Journal of Parallel Programming, June 2006 (IF: 0.289, Q4, Tier A, h5=16). [Preprint] [DOI] [BIB] | ||||
International Peer-Reviewed Conferences |
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| [NOCS'22] | SynFull-RTL: Evaluation Methodology for RTL NoC Designs. N. Leyva, A. Monemi, and E. Vallejo. The 16th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2022), Virtual, October 2022. Conference paper published in IEEE Design & Test. (GGS rating A-, h5=14). [PDF] [DOI] | ||||
| [NOCS'21] | PlugSMART: a pluggable open-source module to implement multihop bypass in Networks-on-Chip. A. Monemi, I. Pérez, N. Leyva, E. Vallejo, R. Beivide and M. Moretó The 15th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2021), Virtual, October 2021. (GGS rating A-, h5=14). [PDF] [DOI] -- BEST PAPER AWARD | ||||
| [ISPASS'20] | BST: A BookSim-based toolset to simulate NoCs with single- and multi-hop bypass. I. Pérez, E. Vallejo, M. Moretó and R. Beivide IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2020), Boston, USA, April 2020. (GGS rating A-, h5=22). [PDF] [DOI] | ||||
| [NOCS'19] | SMART++: Reducing cost and improving efficiency of multi-hop bypass in NoC routers. I. Pérez, E. Vallejo and R. Beivide The 13th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2019), New York, USA, Oct 2019. (GGS rating A-, h5=16). [PDF] [DOI] [BIB] -- BEST PAPER AWARD NOMINEE | ||||
| [HPCA'18] | Architectural Support for Task Dependence Management with Flexible Software Scheduling. E. Castillo, L. Alvarez, M. Moretó, M. Casas, R. Beivide, E. Vallejo, J.L. Bosque and M. Valero The 24th IEEE International Symposium on High-Performance Computer Architecture, Vienna, Austria, Feb 2018. (CORE Tier A*, GGS rating A+, h5=46). [PDF] [DOI] [BIB] | ||||
| [IPDPS'17] | FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks. P. Fuentes, E. Vallejo, R. Beivide, C. Minkenberg and M. Valero The 31st IEEE International Parallel & Distributed Processing Symposium , Orlando, Florida, May 2017. (CORE Tier A, GGS rating A, h5=41). [PDF] [DOI] [BIB] -- BEST PAPER AWARD | ||||
| [ICA3PP'16] | Synthetic Traffic Model of the Graph500 Communications. P. Fuentes, E. Vallejo, J.L. Bosque, R. Beivide, A. Anghel, G. Rodr�guez, M. Gusat and C. Minkenberg. The 16th International Conference on Algorithms and Architectures for Parallel Processing, Granada, Spain, December 2016. (CORE Tier B, h5=13). [DOI] [BIB] | ||||
| [SC'16] | The Mont-Blanc prototype: An Alternative Approach for HPC Systems. N. Rajovic, A. Rico, F. Mantovani, D. Ruiz, J. Oriol, C. Gomez, L. Backes, D. Nieto, H. Servat, X. Martorell, J. Labarta, E. Ayguadé, C. Adeniyi-Jones, S. Derradji, H. Gloaguen, P. Lanucara, N. Sanna, J. F. Mehaut, K. Pouget, B. Videau, E. Boyer, A. Auweter, D. Brayford, D. Tafani, D. Broemmel, R. Halver, J. H. Meinke, R. Beivide, M. Benito, E. Vallejo, M. Valero and A. Ramírez. The International Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing), Salt Lake City, Utah, November 2016. (CORE Tier A, GGS rating A+, h5=48). [PDF] [DOI] [BIB] | ||||
| [IPDPS'16] | CATA: Criticality Aware Task Acceleration for Multicore Processors. E. Castillo, M. Moretó, M. Casas, L. Álvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. L. Bosque, R. Beivide, E. Ayguadé, J. Labarta, and M. Valero. 30th IEEE International Parallel and Distributed Processing Symposium, Chicago, USA, May 2016. (CORE Tier A, GGS rating A, h5=41). [PDF] [DOI] [BIB] | ||||
| [HiPC'15] | On the Use of Commodity Ethernet Technology in Exascale HPC Systems. M. Benito, E. Vallejo, and R. Beivide. 2015 IEEE International Conference on High Performance Computing, Bangalore, India, December 2015. (CORE Tier A, GGS rating B-, h5=14). [PDF] [DOI] [BIB] | ||||
| [HPSR'15] | Performance Optimization of Load Imbalanced Workloads in Large Scale Dragonfly Systems. B. Prisacari, G. Rodríguez, C. Minkenberg, M. García, E. Vallejo, and R. Beivide. 2015 IEEE 16th International Conference on High Performance Switching and Routing, Budapest, Hungary, July 2015. (CORE Tier C, h5=11). [PDF] [DOI] [BIB] | ||||
| [IPDPS'15] | Contention-based Nonminimal Adaptive Routing in High-radix Networks. P. Fuentes, E. Vallejo, M. García, R. Beivide, G. Rodríguez, C. Minkenberg and M. Valero. 29th IEEE International Parallel & Distributed Processing Symposium, India, May 2015. (CORE Tier A, GGS rating A, h5=41). [PDF] [DOI] [BIB] | ||||
| [HiPEAC'15] | Topological Characterization of Hamming and Dragonfly Networks and its Implications on Routing. C. Camarero, E. Vallejo and R. Beivide. HiPEAC 2015 Conference, Amsterdam, January 2015. Conference paper published in ACM TACO, December 2014. [slides] [DOI] [BIB] | ||||
| [ICPP'13] | Efficient Routing Mechanisms for Dragonfly Networks. M. García, E. Vallejo, R. Beivide, M. Odriozola, M. Valero The 42nd International Conference on Parallel Processing (ICPP-42). Lyon, September 2013. (CORE Tier A, GGS rating A-, h5=29). [PDF] [slides] [DOI] [BIB] | ||||
| [HOTI'13] | OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management. M. García, E. Vallejo, R. Beivide, M. Valero, G. Rodríguez The 21st Annual Symposium on High-Performance Interconnects (HOTI-21). San Jose, California, August 2013. (CORE Tier B, GGS rating A-). [PDF] [DOI] [BIB] | ||||
| [PDCAT'12] | Throughput Fairness in Indirect Interconnection Networks. C. Izu, E. Vallejo, The Thirteenth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT). Beijing, China, December 2012. (CORE Tier B, h5=12). [PDF] [DOI] [BIB] | ||||
| [ICPP'12-1] | On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks. M. García, E. Vallejo, R. Beivide, M. Odriozola, C. Camarero, M. Valero, G. Rodríguez, J. Labarta and C. Minkenberg The 41st International Conference on Parallel Processing (ICPP-41). Pittsburgh, USA, September 2012. (CORE Tier A, GGS rating A-, h5=29). [PDF] [DOI] [BIB] -- BEST PAPER AWARD. | ||||
| [MICRO'10] | Architectural support for Fair Reader-Writer Locking. E. Vallejo, R. Beivide, A. Cristal, T. Harris, F. Vallejo, O. Unsal, M. Valero. The 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43). Atlanta, USA, 2010. ( CORE Tier A, GGS rating A+, h5=41). [PDF] [DOI] [BIB] | ||||
| [ACSAC'07] | Implicit Transactional Memory in Kilo-Instruction Multiprocessors. M. Galluzzi, E. Vallejo, A. Cristal, F. Vallejo, R. Beivide, P. Stenstr�m, J. E. Smith, M. Valero. Asia-Pacific Computer Systems Architecture Conference. Seoul, Korea, 2007 (CORE Tier B). [DOI] [BIB] | ||||
| [IPDPS'07] | Mixed-radix twisted Torus Interconnection Networks. J. M. Camara, M. Moretó, E. Vallejo, R. Beivide, C. Martínez, J. Miguel and J. Navaridas. IEEE International Parallel & Distributed Processing Symposium. Long Beach, California, 2007 (CORE Tier A, GGS rating A, h5=41). [PDF] [DOI] [BIB] | ||||
| [ICPS'05] | Implementing Kilo-Instruction Multiprocessors E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith and M. Valero. IEEE Conference on Pervasive Services, ICPS-05. Greece, 2005. (CORE Tier C). [PDF] [DOI] [BIB] | ||||
| [EuroPDP'05] | Practicable Layouts for Optimal Circulant Graphs . E. Vallejo, R. Beivide and C. Martínez. 13th Euromicro Conference on Parallel, Distributed and Network-based Processing. Lugano, Switzerland, 2005. (CORE Tier B, GGS rating B-, h5=19). [PDF] [DOI] [BIB] | ||||
Invited talks |
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| [INA-OCMC'15] | Low-cost Deadlock Avoidance in Direct Interconnection Networks. E. Vallejo. 9th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC). Amsterdam, January 2015. [slides] | ||||
Peer-Reviewed Conferences on Education |
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| [INRED'17] | Aprendizaje autónomo del estudiante apoyado en recursos audiovisuales en el contexto de un Grado de Ingeniería Informática: experiencias con metodologías de enseñanza activas. E. Vallejo, P. Fuentes, M. Benito. III Congreso Nacional de Innovación Educativa y Docencia en Red. Valencia (Spain). July 2017. [DOI] [PDF] | ||||
| [JP'12-1] | Plataforma web para retroalimentación automática en la docencia de ensamblador. C. Martínez, E. Vallejo, P. Fuentes, E. Stafford, J. L. Bosque. Contribution to the XXIII Jornadas de Paralelismo. Elche (Spain). 19-21 September 2012. [PDF] | ||||
| [FECIES'12] | Sistema de Evaluación Automática para Prácticas de Estructura de Computadores. P. Fuentes, C. Mart�nez, E. Vallejo, E. Stafford and J. L. Bosque. Contribution to the IX Foro sobre la evaluación de la calidad de la investigación y de la educación superior (FECIES). Santiago de Compostela (Spain). 12-15-June 2012. [Abstract] | ||||
| [FECIES'11] | Sobre los mecanismos de evaluación de la calidad docente en el EEES. E. Vallejo, C. Martínez. Contribution to the VIII Foro sobre la evaluación de la calidad de la investigación y de la educación superior (FECIES). Santander (Spain). 31-May - 3-June 2011. [Abstract] | ||||
| [EDUCON'10] | Design of an Introductory Networking subject in advance of the European Higher Education Area: Challenges, experiences and open issues. E. Vallejo, E. García. Full paper in the IEEE Annual Engineering Education Conference. Madrid (Spain). 14-16 April 2010. [PDF] | ||||
Intl. Peer-Reviewed Workshops and Poster Abstracts |
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| [NoCArc'23] | OpenPiton Optimizations Towards High Performance Manycores. N. Leyva, A. Monemi, N. Oliete-Escuín, G. López-Paradís, J. Balkind, E. Vallejo, Miquel Moretó and L. Álvarez. 16th International Workshop on Network on Chip Architectures, Toronto, Canada, Oct. 2013. [PDF] [DOI] | ||||
| [NoCArc'18] | Efficient Router Bypass via Hybrid Flow Control. I. Pérez, E. Vallejo, R. Beivide. 11th International Workshop on Network on Chip Architectures, Fukuoka, Japan, Oct. 2018. [PDF] [DOI] [BIB] | ||||
| [NOCS'18] | Improving the Efficiency of Router Bypass. I. Pérez, E. Vallejo, R. Beivide. Poster presented in the 12th IEEE/ACM International Symposium on Networks-on-Chip, Torino, Italy, Oct. 2018. | ||||
| [HiPINEB'18] | Analysis and improvement of Valiant routing in low-diameter networks. M. Benito, P. Fuentes, E. Vallejo, R. Beivide 4th IEEE International Workshop on High-Performance Interconnection Networks Towards the Exascale and Big-Data Era, Vienna, Austria, Feb. 2018. [PDF] [DOI] [BIB] | ||||
| [HiPINEB'17] | Extending commodity OpenFlow switches for large-scale HPC deployments. M. Benito, E. Vallejo, R. Beivide, C. Izu 3rd IEEE International Workshop on High-Performance Interconnection Networks Towards the Exascale and Big-Data Era, Austin, USA, Feb. 2017. [PDF] [DOI] [BIB] | ||||
| [HiPINEB'15] | Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns. P. Fuentes, E. Vallejo, C. Camarero, R. Beivide, M. Valero 1st IEEE International Workshop on High-Performance Interconnection Networks Towards the Exascale and Big-Data Era, Chicago, USA, Sept. 2015. [PDF] [DOI] [BIB] | ||||
| [IWSG'15] | TraceRep: Gateway for Sharing and Collecting Traces in HPC Systems. I. Pérez, E. Vallejo, J. L. Bosque. Seventh International Workshop on Science Gateways, Budapest, Hungary, June 2015. [PDF] [DOI] [BIB] | ||||
| [ACACES'14] | On the use of contention information for adaptive routing. P. Fuentes, E. Vallejo, M. García, R. Beivide. Poster presented in the Tenth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Fiuggi, Italy, July 2014. | ||||
| [INA-OCMC'14] | Performance implications of remote-only load balancing under adversarial traffic in Dragonflies. B. Prisacari, G. Rodriguez, M. García, E. Vallejo, R. Beivide, C. Minkenberg. The 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC). Vienna, Austria, 22 January 2014. [PDF] | ||||
| [INA-OCMC'13] | Global Misrouting Policies in Two-level Hierarchical Networks. M. García, E. Vallejo, R. Beivide, M. Odriozola, C. Camarero, M. Valero, G. Rodriguez, J. Labarta. The 7th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC). Berlin, Germany, 23 January 2013.[PDF] [BIB] | ||||
| [ICPP'12-2] | Comparison study of scalable and cost-effective interconnection networks for HPC. P. Fuentes, E. Vallejo, C. Martínez, M. García, R. Beivide. Poster presented in the 41st International Conference on Parallel Processing (ICPP 2012). Pittsburgh, PA, USA, 10-15 September 2012. (Tier A). [PDF] [BIB] | ||||
| [EPHAM'08] | Towards fair, scalable, locking. E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal and M. Valero. 1st Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008). April 6, 2008, Boston, Massachusetts, USA. [PDF] | ||||
| [TRANSACT'08] | Hybrid Transactional Memory to accelerate safe lock-based transactions. E. Vallejo, T. Harris, A. Cristal, O. Unsal, M. Valero. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008). February 23, 2008, Salt Lake City, Utah, USA. [PDF] . Abstract published in ACM SIGPLAN Notices, Volume 43, Issue 5 (May 2008). | ||||
| [ACACES'06] | Chip Multiprocessors with Implicit Transactions. E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith and M. Valero. Poster presented in the Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, L’Aquila, Italy, 23-29th July 2006. [abstract] | ||||
| [ACACES'05-2] | New Layouts for Midimew Interconnection Networks. E. Vallejo, C. Martínez and R. Beivide. Poster presented in the First International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, L’Aquila, Italy, 24-30th July 2005. [abstract]. | ||||
| [ACACES'05-1] | Hierarchical Gaussian Topologies. M. Moretó, C. Martínez, R. Beivide, E. Vallejo and M. Valero. Poster presented in the First International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, L’Aquila, Italy, 24-30th July 2005. [abstract]. | ||||
| [MGRID'05] | Gaussian Interconnections for On-chip Networks. R. Beivide, C. Martínez and E. Vallejo. 1st Microgrid Workshop, University of Amsterdam, The Netherlands, 1st and 2nd of July 2005. [draft]. | ||||
Other Conference Contributions |
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| [ISUM'19] | Lagarto I RISC-V Multi-Core: Research Challenges to build and integrate a Network-on-Chip. N. Leyva, I. Pérez, C. Hernández-Calderón, E. Vallejo, M. Moretó, R. Beivide, M. Ramírez-Salinas, L. Villa-Vargas 10th International Supercomputing Conference in Mexico (ISUM 2019), Monterrey, Mexico, 2019. [DOI] | ||||
| [AusPDC'19] | Impact of Network Fairness on the Performance of Parallel Systems. C. Izu, E. Vallejo 17th Australasian Symposium on Parallel and Distributed Computing (AusPDC 2019), Sysney, Australia, 2019. (CORE Tier: Australasian) [PDF]. | ||||
| [EMiT'16] | Analysing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures. I. Pérez, E. Castillo, R. Beivide, E. Vallejo, J.L. Bosque, Miquel Moretó, M. Casas, and M. Valero EMerging Technology Conference, Barcelona, Spain, June 2016. | ||||
| [JP'14] | TraceRep: Herramienta de extracción y gestión de trazas en sistemas HPC, I. Pérez, E. Vallejo, J. L. Bosque. XXV Jornadas de Paralelismo. Valladolid (Spain). 17-19 September 2014. | ||||
| [HPC'13] | Task Mapping in Rectangular Twisted Tori. C. Camarero, E. Vallejo, C. Martínez, M. Moretó and R. Beivide, The 21st High Performance Computing Symposium (HPC'13). San Diego, CA, USA, April 2013. | ||||
| [JP'12-2] | Bubble Flow Control in High-Radix Hierarchical Networks, M. García, E. Vallejo, R. Beivide, M. Odriozola, C. Camarero, M. Valero, G. Rodríguez, J. Labarta and C. Minkenberg. XXIII Jornadas de Paralelismo. Elche (Spain). 19.21-September 2012. | ||||
| [JP'11] | Peripheral twists for torus topologies with arbitrary aspect ratio, E. Vallejo, M. Moretó, C. Martínez, and R. Beivide. XXII Spanish Parallelism Conference, La Laguna, Spain, Sept. 2011. | ||||
| [JP'05-1] | KIMP: Multicheckpointing Multiprocessors, E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith and M. Valero. XVI Spanish Parallelism Conference, Granada, Spain, Sept. 2005. | ||||
| [JP'05-2] | Hierarchical Topologies for Large-scale Two-level Networks, C. Martínez, E. Vallejo, M. Moretó, R. Beivide and M. Valero. XVI Spanish Parallelism Conference, Granada, Spain, Sept. 2005. | ||||
| [JP'05-3] | Gaussian Interconnection Networks, C. Martinez, R. Beivide, E. Vallejo and C. Izu. XVI Spanish Parallelism Conference, Granada, Spain, Sept. 2005. | ||||
| [ACM Portal] - [IEEE Computer Society] - [IEEE Xplore] - [DBLP] - [BSC-MS Research Centre] - [Google Scholar] | |
Note: Conference and journal rankings, if variable, were correct at the time of inserting into this page.